The present invention relates generally to package construction of integrated circuits. More specifically, but without limitation thereto, the present invention relates to the construction of an integrated circuit package for a flip chip ball grid array (BAG).
FIG. 1 is a side view diagram of a typical flip chip ball grid array package 100 of the prior art. Shown are a stiffener 102, a heat spreader 104, a die 106, a laminated substrate 108, wafer bumps 110, an under fill 112, a thermally conductive layer 114, solder balls 116, and a second level package 120.
In traditional flip chip package design, the die 106 has a standard thickness of 725 microns and is electrically connected to the laminated substrate 108 by the wafer bumps 110, which are typically made of a eutectic solder. The spaces between the wafer bumps 110 are filled with an adhesive under fill 112 after bonding the die 106 to absorb stresses on the die 106 due to a mismatch in the coefficient of thermal expansion (CITE) between the die 106 and the laminated substrate 108. The under fill 112 is typically an epoxy material that flows and fills the gap between the laminated substrate 108 by capillary action, and is cured after filling the gaps between the wafer bumps 110.
The stiffener 102 and the heat spreader 104 typically have the same area as the flip chip plastic ball grid array package 100. The stiffener 102 is attached to the substrate 108 to protect the flip chip ball grid array package 100 from flexural damage. The heat spreader 104 is attached to the stiffener 102 to conduct heat away from the die 106 though the thermally conductive layer 114. The flip chip ball grid array package 100 is mounted on the second level package 120 by the solder balls 116. The solder balls 116 have a typical width of about 610 microns, while the wafer bumps 110 have a typical width of only about 89 microns.
There are several problems and disadvantages with this approach, for example, inherent mismatch of the coefficient of thermal expansion of the die 106 (typically about 3.5 parts per million per degree Kelvin) with that of the laminated substrate 108 (typically about 16 parts per million per degree Kelvin) and poor adhesion between the adhesive under fill 112 and the passivation. The passivation is a thin film coating on the active side of the die 106 to protect the circuits on the die 106 from the environment. Typical passivation coatings are Sin, polyamide, and BCB. The mismatch of the coefficient of thermal expansion and the poor adhesion leads to delamination of the die 106 from the under fill 112 and subsequent cracking of the wafer bumps 110. Filling the small gaps between the wafer bumps 110 with the under fill 112 also becomes increasingly difficult due to packaging using increasingly smaller bump pitch. As the bump pitch becomes smaller, air bubbles are introduced in the under fill 112 that propagate cracks in the wafer bumps 110. Further, there may be flux contamination that leads to the delamination of the under fill 112.
The present invention advantageously addresses the needs above as well as other needs by providing a method for making a flip chip ball grid array (BAG) package that reduces mismatch of a coefficient of thermal expansion (CITE).
In one embodiment, the invention may be characterized as a flip chip ball grid array package that includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
In another embodiment, the present invention may be characterized as a method for making a flip chip ball grid array package that includes the steps of reducing the thickness of a die from a wafer thickness to make a thin die; forming a plurality of thin film layers on the thin die surrounding vias wherein each thin film layer has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of a substrate; forming a plurality of wafer bumps on the vias to make electrical contact with the thin die; and bonding the thin die to the substrate to make electrical contact between the wafer bumps and the substrate.
In yet another embodiment, the present invention may be characterized as a method for making a flip chip ball grid array package that includes the steps of reducing the thickness of a die from a wafer thickness to make a thin die; forming a plurality of wafer bumps on the thin die; forming a plurality of thin film layers on a substrate surrounding each of a plurality of contact pads on the substrate wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and bonding the thin die to the substrate to make electrical contact between the plurality of wafer bumps on the thin die and the plurality of contact pads on the substrate respectively.